Friday, December 12, 2008

Cadence releases Accelerated Parallel Simulator for Analog/MS IC Designs

Much of the news concerning Cadence Design these days has not been good, but today’s announcement bucks that run of bad corporate-related news. Today the company announced the availability of an Accelerated Parallel Simulator (APS) for its Virtuoso product. The majority of RFIC designers use the Virtuoso suite for IC circuit design/simulation and in particular its Virtuoso Spectre® Circuit Simulator, which specifically solves large, complex analog and mixed-signal designs across all process nodes. The new simulator adds a breakthrough parallel circuit solver, along with a newly architected engine to give users access to multiprocessing computing platforms.

The result is an accurate circuit simulator that uses models which are identical to the Virtuoso Spectre Circuit Simulator, delivering significantly improved single-thread performance and scalable multi-thread performance. The Virtuoso Accelerated Parallel Simulator improves convergence and capacity for designs with hundreds of thousands of transistors, reducing design and verification time in most cases from weeks to hours. Company spokesmen boosted 20.6 times performance boost over traditional SPICE simulators, which enabled users to verify and detect multiple design issues.

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